Shared memory architecture in GPS signal processing

ABSTRACT

A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

FIELD OF INVENTION

[0001] This invention relates to the field of GPS receivers.

BACKGROUND OF INVENTION

[0002]FIG. 1 illustrates a typical GPS radio receiver 10, while FIG. 2provides a general flow chart illustrating the general operations of GPSreceiver 10 such as a satellite signal acquisition, tracking, orre-acquisition, and navigational processing. As illustrated in thesimplified block diagram of a typical GPS receiver 10 shown in FIG. 1, asignal processing block 20 is provided to perform satellite signalacquisition and processing on a digitized IF signal 19 received viareceiver antenna 12. Signal processing block 20 typically performs atwo-dimensional search for a satellite signal, in time (code phase) andfrequency. To decrease the amount of time needed for GPS signalacquisition in time and frequency domains, a massively parallelarchitecture is usually required for searching in parallel a largenumber of code positions and frequency uncertainties. In the code phasesearch, the required number of code positions is directly related toinitial time uncertainty. A large number of corellators allows a quick,parallel search of many code positions. In the frequency search, a largenumber of frequency bins architecture speeds up searching multiplefrequency uncertainties in parallel, thereby reducing the total time forsearch.

[0003] As illustrate in FIG. 1, signal processing 20 consists of threefunctional stages: a first stage consists of channel correlation signalprocessing 22 that compares (or correlates) digitized signal 19 with alocally generated code that attempts to replicate the P or C/A codegenerated by a satellite. The replica code searches a “space” thatconsists of the unique codes generated by the different satellites, thetemporal position of the code being sent at any given time, and theDoppler frequency offset caused by the relative motion of the satelliteand user. Generally, correlator signal processing 20 can performparallel correlations with multiple code/position/doppler combinationssimultaneously in a multiple channel fashion, usually up to 12. The nextfunctional stage of signal processing 20 comprises tracking processing24, typically provided by a tracking processing CPU. The trackingprocessing CPU uses correlator information from correlatror signalprocessing 22 to ascertain the probability of correctness of acode/position/doppler combination and to “follow”, or track, that signalonce it is found. Tracking processing unit 24 includes having thetracking CPU program the correlator signal processing unit 22 where tosearch for a GPS satellite signal. Once a signal is found and lockedonto, the tracking CPU also extracts the 50 Hz modulated data thatcontains navigation information transmitted by the GPS satellite.Finally, a navigation processing unit 26, comprising a navigationprocessing CPU, uses data collected by the correlator signal processing22 and tracking processing 24 to perform the calculations to determinethe user's position, velocity, and time

[0004] In the typical GPS signal processing 20, an associated anddedicated memory unit is coupled to each functional unit stage. Thus,Correlator signal processing 22 is typically coupled to an associateddedicated correlation processing memory unit 28 shown in FIG. 1.Coherent and non-coherent I & Q samples are stored in correlationprocessing memory 28 received from correlator signal processing 22.Tracking processing unit 24 is coupled to a tracking unit memory 30 tostore the code, data, and parameters utilized by the tracking processorCPU for acquisition and tracking processing such as, for example,carrier loops, code loops, code lock detect, costas lock detect, bitsynchronization, data demodulation. Navigation processing unit 26 iscoupled to a navigation processing memory 32 for storing the code anddata for the navigation processing CPU, such as calculation of positionand time.

[0005] Thus, in operation, typical GPS receiver 10 requires significanthardware and memory to search, utilizing a large number of correlatorsand multiple frequency bins to implement. For example, an 8 frequencybin search should reduce the search time by a factor of 8 but it willrequire 4 times the memory to store the coherent integration samples and8 times the memory to store the non-coherent integration samples. Inorder to achieve low cost, commercial GPS receiver architectures aredeterred from using massively parallel architectures to avoid the costof massively parallel implementation. There is therefore a need for aGPS signal processing architecture that minimizes the costly memoryrequirement and still achieves extremely fast signal acquisition.

SUMMARY OF INVENTION

[0006] A shared memory architecture for a GPS receiver is provided,wherein a processing memory is shared among the different processingfunctions, such as the correlator signal processing, trackingprocessing, and other applications processing. The shared memoryarchitecture within the GPS receiver provides the memory necessary forsignal processing operations, such as the massively parallel processing,while conserving memory cost by re-using that same memory for other GPSand non-GPS applications. The shared memory architecture for a GPSreceiver provided in accordance with the principles of this inventionthereby minimize the costly memory requirement often required ofextremely fast signal acquisition of a GPS receiver.

BRIEF DESCRIPTION OF DRAWINGS

[0007]FIG. 1 is a block diagram describing a prior art GPS receiver.

[0008]FIG. 2 is a flowchart describing the operation of a GPS receiver.

[0009]FIG. 3 is a block diagram describing the shared memoryarchitecture of the invention.

[0010]FIG. 4 is a block diagram describing the channel correlator signalprocessing.

[0011]FIG. 5 is a block diagram describing IQRAM and IQSQRAM arbitratorin channel correlator signal processing.

[0012]FIG. 6 is a block diagram describing a memory map for IQRAM forthe channel correlator processing.

[0013]FIG. 7 is a block diagram describing a memory map for IQSQRAM inacquisition for the channel correlator processing.

[0014]FIG. 8 is a block diagram describing a memory map for IQSQRAM intracking/reacquisition mode.

[0015]FIG. 9 is a block diagram describing an example of a two way setassociative cache memory map for both tracking and navigationprocessing.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT(S)

[0016]FIG. 3 shows a shared memory architecture 100 for a GPS receiver,wherein a signal processing memory 144 is shared among different signalprocessing functional units, such as a correlator signal processing unit122, tracking processing 124 and applications processing unit 126. FIG.4 shows a more detailed functional block diagram of processing memory144 comprising an IQRAM 53 and an IQSQRAM 59. FIG. 4 further illustratesshared memory architecture 100 in operation, as an illustration, such asduring operations of channel correlator signal processing 122.

[0017] In operation, an IQ separator and down converter 46 samples asatellite IF signal 19 and separates signal 19 into a pair of I and Qsignals 47. I and Q signal pair 47 is down converted to a basebandfrequency before being provided to a Doppler rotator 48, which providesDoppler rotation of IF signal pair 47. Both carrier phase and carrierFrequency are programmed in the Doppler rotator 48 by a trackingprocessing CPU of tracking processing unit 124 of FIG. 3. As shown inFIG. 4, correlator 50 receives the Doppler rotated I and Q signal pair49 and correlates signal pair 49 with a replica I and Q code produced bya code generator 52. An IQ accumulator 54 receives both I and Q samplesfrom correlator 50 and accumulates the samples over a coherentintegration period. The accumulated results are stored separately in anIQRAM 53. The multiple frequency bin correlator 56 then receives I and Qdata provided from IQ accumulator 54 and performs an accumulation on theresults of the square root of the sum of I-squared plus Q-squared for aperiod of time specified as non-coherent integration. The accumulationresults are then stored in an IQSQRAM memory 59 of processing memory144.

[0018]FIG. 5 further illustrates a more detailed block diagram of anIQRAM arbitrator 60 and an IQSRAM arbitrator 62 provided to arbitrateuse of IQRAM 53 and IQSQRAM 59. FIG. 5 illustrates the IQRAM and IQSQRAMarbitrator 60 and 62 that control access to shared memory IQRAM 53 andIQSQRAM 59, i.e., such as arbitrating memory use between channelcorrelator signal processing 122 and the other functions seeking accessto memory 144. For the IQRAM arbitrator logic 60, the multiple memoryaccess sources comprise the coherent integration of I and Q data 64 fromthe output of coherent integration function 64 of correlator 122, themultipath/early-late processing 66 (i.e., for sampling data used formultipath mitigation by the tracking processor), the cache tag and datafrom the cache controller 68 (i.e. used to speed up memory accesses forall the signal processing, including tracking processing and navigationprocessing), and any application processing. In this example, duringtracking, the IQRAM arbitration logic 60 arbitrates the multiple sourcesseeking access to IQRAM 53′. The IQSQRAM arbitrator 62 includescontrolling access from the non-coherent integration of I and Q signals74, access to parameters stored for the tracking loops 76, multiplefrequency bin correlation 78, the convolution decoder 80 (used for aspecial differential GPS function), and any application processingfunctions. The arbitrator, such as the IQSQRAM arbitrator 150,arbitrates the multiple sources seeking access to the IQSQRAM 59.

[0019]FIG. 6 shows an example of the memory map of the IQRAM 53 duringour tracking operation example. There are three different addressesranges for three types of memory sources: the coherent integration of Iand Q data from the correlator outputs (multiple samples in acquisitionmode, single sample in track/re-acquisition mode), themultipath/early-late sample data, and the cache tag/data. For thisexample, in satellite acquisition mode the whole address space of 0x000though 0x1f7 is used to store the multiple sample (in this case four)coherent integrations needed to search multiple frequency binssimultaneously. In track, or reacquisition modes, however, only a singlesample needs to be collected instead of four. Thus, intrack/reacquisition modes, the coherent integration I and Q data isstored only in the address range from 0x000 to 0x077. This frees up theremaining space to be used for other functions. The multipath/early-latesampling data is stored in the address rage from 0x080 to 0x0ff. Thecache tag/data for tracking or navigation processing is stored in therange from 0x100 to 0x1ff. FIG. 9 shows a structure for a 2 way setassociative cache implementation of processing memory 144. The cache canbe used as the instruction and data cache for the tracking andnavigation processing functions to speed them up. The memory region usedas cache can alternatively be used as fast local RAM for data storage bythe tracking processor or applications processor. Thus, same areas ofthe address map are shared by multiple functions, including othernon-GPS applications, such as navigation processing, GPS locationprocessing, wireless networking protocol processing, and otherapplication processing that would be desirable to incorporate into GPSreceiver 100.

[0020]FIG. 7 and FIG. 8 show the memory map for IQSQRAM 59 for other GPSfunctions, such as acquisition (or re-acquisition). The memoryrequirements once again are different for acquisition mode andtrack/reacquisition modes. In acquisition mode, 1920 words in addressrange of 0x000 to 0x77f are used to store noncoherent accumulations. Intrack/reacquisition modes, however only 240 words stored in addressrange 0x000 to 0x0ef are needed to store the noncoherent accumulations.This frees up the remaining space for other functions. In this examplethe other functions include convolutional decoder parameters and data,and expanded tracking processor parameters and data.

[0021] FIGS. 7-8 illustrates sample memory mapping for memory IQSQRAMduring different modes. The memory mapping of IQRAM 53 and IQSQRAM 59 ofprocessing memory 144 as illustrated in FIGS. 7-8 is a sampleimplementation. It is understood that this shared memory mapping in GPSreceiver 100 can be extended to process other applications performed bythe GPS receiver, such as navigation processing, GPS locationprocessing, processing wireless networking protocols, to just name afew. It should be understood that the shared memory architecture 100,such as illustrated with reference to FIGS. 3-9 can be applied to otherGPS receiver applications contemplated as being within a GPS receiver.The shared memory architecture within the GPS receiver provides thememory necessary for signal processing operations, such as the massivelyparallel processing, while conserving memory cost by re-using that samememory for other GPS and non-GPS applications. The shared memoryarchitecture for a GPS receiver provided in accordance with theprinciples of this invention thereby minimize the costly memoryrequirement often required of extremely fast signal acquisition of a GPSreceiver.

[0022] Foregoing described embodiments of the invention are provided asillustrations and descriptions. They are not intended to limit theinvention to precise form described. In particular, Applicant(s)contemplate that functional implementation of invention described hereinmay be implemented equivalently in hardware, software, firmware, and/orother available functional components or building blocks. Othervariations and embodiments are possible in light of above teachings, andit is thus intended that the scope of invention not be limited by thisDetailed Description, but rather by claims following.

What is claimed is:
 1. A shared memory architecture for a receiversystem comprising a memory space shared commonly by two or more receiverfunctions comprising a correlator signal processing, a trackingprocessing and an application processing unit to minimize memory spacerequirement.
 2. The shared memory architecture of claim 1 wherein thecommonly shared memory space functions as a coherent and a noncoherentintegration memory for the correlation processing during signalcorrelation mode while the commonly shared memory space is also used forone or more other receiver processing functions during one or more otherreceiver operation modes.
 3. The shared memory architecture of claim 1wherein the commonly shared memory space comprises a first memorysection and a second memory section, wherein the first memory sectionfunctions as a coherent and the second memory section as a noncoherentintegration memory for a correlation processing during signalcorrelation mode while the shared memory space is also used for one ormore other receiver processing functions during one or more otherreceiver operation modes.
 4. The shared memory architecture of claim 1wherein the commonly shared memory space comprises a first memorysection used as the system memory for a fast local memory or systemcache during tracking or application processing.
 5. The shared memoryarchitecture of claim 1 wherein the application processing comprisenavigation processing.
 6. The shared memory architecture of claim 1wherein the application processing comprise GPS location processing. 7.The shared memory architecture of claim 1 wherein the applicationprocessing comprise wireless networking protocol processing.